Vikram Chauhan
Independent Researcher
India
Abstract
The increasing demand for portable and battery-powered devices necessitates the development of low-power Analog-to-Digital Converters (ADCs) with high accuracy and efficiency. This paper explores the design and implementation of low-power CMOS ADC architectures suitable for portable applications. It emphasizes techniques such as capacitor scaling, power gating, and advanced circuit topologies to reduce power consumption without compromising performance. A comparative analysis of successive approximation register (SAR), pipelined, and sigma-delta ADCs is presented. Simulation results validate the proposed design approaches in a 180 nm CMOS process technology, demonstrating a balance between power, speed, and resolution. The study provides insights for engineers to develop optimized ADCs critical for modern portable electronics.
Keywords
Low-power ADC, CMOS, portable devices, successive approximation register, pipelined ADC, sigma-delta ADC, power optimization.
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