Siddharth Kapoor
Independent Researcher
India
Abstract
In the domain of portable electronic systems, energy efficiency remains a critical design objective to prolong operational life and reduce thermal dissipation. Low-power CMOS circuit design techniques enable significant reductions in dynamic and static power consumption by optimizing transistor sizing, threshold voltage selection, voltage scaling, and architectural choices without compromising performance requirements. This manuscript presents a comprehensive study on the design of low-power CMOS circuits for portable devices, detailing fundamental techniques such as multi-threshold CMOS (MTCMOS), power gating, clock gating, dynamic voltage and frequency scaling (DVFS), subthreshold operation, and adaptive body biasing. Through selected case studies involving a wearable health monitor, a smartphone audio amplifier, and an RFID sensor node, the efficacy of these techniques is demonstrated via SPICE simulations and layout-level estimations. The methodology integrates schematic capture, device modeling, parasitic extraction, and performance validation under worst-case and typical-case operating conditions. Results show up to 65% reduction in total energy per operation and leakage currents below 100 nA per gate for subthreshold designs. Conclusions highlight trade-offs among power, area, and speed, and recommend design practices aligned with technology and tools available up to 2018. Ten references up to 2018 are provided, reflecting seminal works and industry benchmarks.
Keywords
Low-power CMOS, portable devices, multi-threshold CMOS, dynamic voltage scaling, power gating, subthreshold operation
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