Rudra Jagtap
Independent Researcher
India
Abstract
This manuscript investigates strategies for reducing power consumption in VLSI circuits by leveraging advanced CMOS‐based design techniques prevalent up to 2015. We review low‐power design principles—including multi‐threshold voltage (MTCMOS), power gating, dynamic voltage scaling (DVS), and subthreshold operation—and analyze their trade‐offs in performance, area, and leakage. Three industry‐relevant case studies illustrate practical implementations: an ARM‐core subthreshold processor, a power‐gated SRAM macro, and a dynamically scaled DSP accelerator. Methodology encompasses SPICE‐level modeling, RTL synthesis in 65 nm CMOS, and power characterization with Synopsys PrimeTime PX. Results demonstrate up to 80 % leakage reduction and 40 % dynamic power savings at minimal performance penalty. We conclude that a judicious combination of threshold tuning and voltage management yields significant energy efficiency gains, guiding future CMOS‐based low‐power VLSI designs within the 2015 technology landscape.
Keywords
Low-power VLSI, CMOS, power gating, multi-threshold, dynamic voltage scaling, subthreshold operation
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