Rucha Srivastava
Independent Researcher
India
Abstract
This manuscript presents the implementation of error correction codes (ECC) using the Viterbi algorithm as of 2015, focusing on convolutional code structures, hardware realization options, and performance evaluation over additive white Gaussian noise (AWGN) channels. We review foundational literature through 2015, derive design criteria for rate–constraint code selections, implement the Viterbi decoder on FPGA and DSP platforms available by 2015, and conduct statistical analysis of bit-error rate (BER) versus signal-to-noise ratio (SNR). Results demonstrate that a rate-1/2, constraint-length 7 convolutional code decoded via Viterbi achieves a 5 dB coding gain at BER = 10⁻⁵. Identified research gaps include low-power decoder design and adaptive code rate techniques. Ten references up to 2015 are provided.
Keywords
Viterbi algorithm, convolutional codes, FPGA implementation, bit-error rate, AWGN
References
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