Aditi Brahmbhatt
Independent Researcher
India
Abstract
This manuscript presents a comprehensive study on the VLSI implementation of a finite impulse response (FIR) filter using field-programmable gate array (FPGA) technology available up to 2018. The work details the design flow from high-level filter specification and coefficient quantization through hardware description language (HDL) coding, synthesis, place-and-route, and timing verification. Key performance metrics—such as resource utilization, maximum operating frequency, and power consumption—are evaluated across multiple synthesis runs. Statistical analysis is performed to quantify implementation variability. The proposed design demonstrates low latency, efficient area usage, and suitability for real-time signal processing in embedded systems. Research gaps and recommendations for future improvements are also identified.
Keywords
VLSI, FPGA, FIR filter, HDL synthesis, resource utilization, timing analysis
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